(a) Field of the Invention
The present invention relates to a semiconductor memory device having a reduced area for a resistor element in a memory cell.
(b) Description of the Related Art
A dynamic random-access memory (DRAM) is a typical semiconductor memory device, which includes a memory cell area receiving therein a plurality memory cells arranged in a matrix, and a peripheral area receiving therein a control circuit for controlling the read/write operation for the memory cells and a power supply circuit having a plurality of resistor elements.
Referring to FIG. 1 showing a conventional DRAM, each memory cell in the memory cell array includes a cell transistor having source/drain regions 13 disposed in a surface region of a silicon substrate 11 separated by a LOCOS field oxide film 12, and a 200-nm-thick gate electrode 15 disposed above the silicon substrate 11 with an intervention of a 8-nm-thick gate oxide film not shown in the figure. In this text, all the dimensions used herein are approximate values if not specifically recited.
The gate electrode 15 has a laminate structure including a 100-nm-thick polycrystalline silicon (polysilicon) and a 100-nm-thick tungsten silicide film. In the case of 256 Mbit DRAM, the gate width is 0.22 .mu.m and the space between the gate electrodes 15 is 0.28 .mu.m.
The source/drain regions 13 are electrically connected to respective overlying electrodes via first and second contacts 19 and 20. These contacts 19 and 20 are implemented by a phosphorous-doped polysilicon film, which is electrically insulated from the gate electrodes 15 by a 100-nm-thick cap oxide film 17 overlying the gate electrodes 15 and a 60-nm-thick side wall oxide filmS 18 disposed at the side walls of the gate electrodes 15.
In the case of 256 Mbit DRAM, the widths of the contacts 19 and 20 are 0.28 .mu.m and the space between the contacts 19 and 20 are 0.22 .mu.m, as viewed in a section passing perpendicularly to the gate electrodes 15.
The first contact 19 is electrically connected to a bit line 23 via a polysilicon plug 22, whereas the second contact 20 is electrically connected to a capacitor electrode 25 implemented by a 800-nm-thick phosphorous-doped polysilicon film. A capacitor dielectric film (not shown) and a 150-nm-thick cell plate electrode 26 made of phosphorous-doped polysilicon are consecutively formed on the capacitor electrode 25, and a third level interlayer dielectric film 27 is formed covering the entire surface including the cell plate electrode 26. The capacitor dielectric film is implemented by a 7-nm-thick silicon nitride film.
On the other hand, a power supply section including a plurality resistor elements is provided on the peripheral region of the memory device. In the power supply section, a first level interlayer dielectric film 32 and a second level interlayer dielectric film 33 are consecutively formed on the LOCOS field oxide film 12, and the resistor element 21 implemented by a 100-nm-thick phosphorous-doped polysilicon film is formed on the second level interlayer dielectric film 33.
The cell plate electrode 26 and the resistor element 21 are formed from a common polysilicon film formed in a lithographic step. In the case of 256 Mbit DRAM, the resistor element 21 has a line width of 0.8 .mu.m and a line space of 0.8 .mu.m. The resistor element 21 has a pair of lead elements 28 at which the resistor element 21 is electrically connected to overlying interconnects via contacts 29.
FIGS. 2A to 2E consecutively show a fabrication process for the DRAM of FIG. 1. In FIG. 2A, a gate oxide film not shown in the figure is formed to a thickness of 8 nm after forming a field oxide film 12 on a silicon substrate 11, followed by formation of gate structures each including a gate electrode 15 and a cap oxide film 17 and source/drain diffused regions 13 in combination with the gate structures. Each gate structure includes 100-nm-thick silicon oxide film/100-nm-thick tungsten silicide film/100-nm-thick polysilicon film, for example, as viewed from the top.
Thereafter, as shown in FIG. 2B, a 60-nm-thick oxide film 35 is grown over the entire surface, followed by etch-back thereof in the memory cell area. Subsequently, a 150-nm-thick phosphorous-doped polysilicon film is formed, followed by patterning thereof to leave contacts 19 and 20 at specified locations in the memory cell area. Further, as shown in FIG. 2C, a first level interlayer dielectric film 32 is formed over the entire surface, followed by a photolithographic etching thereof to form via holes for exposing the first contact 19, and subsequent deposition of polysilicon to form bit lines 23 and a contact plug in contact with the contact 19.
Thereafter, as shown in FIG. 2D, a second level interlayer dielectric film 33 is formed over the entire surface, followed by photolithographic etching thereof to form a via hole exposing the second contact 20, deposition of a 800-nm-thick phosphorous-doped polysilicon film, and patterning thereof to form a capacitor electrode 25 in contact with the second contact 20.
Subsequently, as shown in FIG. 2E, a 8-nm-thick silicon nitride film implementing a capacitor dielectric film and a 150-nm-thick phosphorous doped polysilicon film are consecutively deposited, followed by patterning thereof by a photolithographic etching step to form a cell plate electrode 26 in the memory cell area and a resistor element 21 in the peripheral area in the common process.
After a third level interlayer dielectric film 27 is formed over the entire surface, via holes are formed for connecting the cell plate electrode 26 and the resistor element 21 with overlying electrodes, thereby obtaining the structure shown in FIG. 1.
In the conventional DRAM as described above, there is a problem in that the cell plate electrode 26 and the resistor element 21, implemented by a common level interconnect layer, causes a larger occupied area for the resistor element 21, which hinders the DRAM from being formed in a smaller design rule.
Specifically, the polysilicon film for implementing the cell plate electrode 26 is generally doped with phosphorous at as high as 1.0.times.10.sup.20 atoms/cm.sup.3 so as to suppress generation of depletion layer in the capacitor element. In this case, the sheet resistance of the polysilicon film is as low as 50 .OMEGA./.DELTA.. Even in this low sheet resistance of the polysilicon film, the portion of the polysilicon film implementing the resistor element 21 must have a resistance as high as 1000 k.OMEGA., for example. This high resistance may be obtained by the portion of the polysilicon film having a width of 0.8 .mu.m and a length as large as 16 mm. The large length for the resistor element 21, however, requires a large occupied area, as shown in FIG. 3, wherein the resistor element 21 together with an associated pair of lead elements 28 is shown in a top plan view.
In order to reduce the occupied area for the resistor element 21, the resistor element 21 should have a smaller width for increasing the resistance of the resistor element 21 obtained from the polysilicon film. However, the smaller width requires an accurate patterning of the polysilicon film, which necessitates an increase of the cost for the DRAM because of a specific exposure step for a fine patterning.
In addition, in the DRAM as described above, the capacitor insulation layer is implemented by a silicon nitride film, which has a smaller dielectric constant and thus provides only a small capacity per unit area for the capacitor element. If the silicon nitride film is replaced by a ferroelectric material having a high dielectric constant, such as a tantalum oxide film, for obtaining a larger capacity per unit area for the capacitor element, the material for the cell electrode should be changed to a refractive metal. This again reduces resistivity of the material for the resistor element and causes a larger occupied area for the resistor element.
In short, in the conventional DRAM, it is difficult to reduce the occupied area for the resistor element disposed in the peripheral area of the DRAM, without an increase in the fabrication cost therefor.